It is known to provide data processing systems which contain a number of state retention circuits configured to hold respective state values at respective nodes of the data processing system when the data processing system enters a low power mode. This enables the data processing system to later exit the low power mode and to continue its data processing operations from the configuration in which it entered that low power mode. For example, these state retention circuits may be provided by so-called “balloon latches”, which can be provided with their own supply voltage and configured to have characteristics desirable in lowering the data processing system's power consumption during the low power mode (e.g. low current leakage).
It is also known that such state retention circuits can be connected together in series such that a scan path is formed. Such a scan path (or “scan chain”) enables shift-register operation in which test pattern state can be loaded into and unloaded from the state retention circuits to allow automatic test pattern generated (ATPG) production test vectors to be used to test the logic circuits of the data processing apparatus connected to the state retention circuits.
As process geometries for forming integrated circuits become increasingly small, these circuits (and in particular in the present context the state retention circuits) become increasingly vulnerable to soft errors, which may have a number of causes such as ionising radiation, thermal variation, device aging and so on. Of course, if such errors occur in the state retention circuits, then the respective state values held by those state retention circuits cannot be relied upon, meaning that the data processing circuitry cannot be guaranteed to continue its data processing operation as desired when it exits the low power mode. One approach to providing resistance to such soft errors is to ensure that a safe margin is provided in the voltage supplied to the state retention circuits over their minimum operating voltage in order to increase their resistance to such soft errors. However, given the desire to push the power consumption of such data processing systems ever lower, the additional power consumed within this safe margin is undesirable. Another approach to supporting the integrity of the state retention circuits has been the provision of voltage-sensitive “canary circuits” provided in association with each of the state retention circuits, in which a deliberately skewed shadow state retention structure is configured to fail before the actual state retention circuit. However, the additional circuit area and power taken up by such canary circuits is undesirable.
Accordingly, it would be desirable to provide an improved technique for supporting the state integrity of such state retention circuits.
By way of background information, the following documents discuss related aspects of the prior art:    1) “Designing for State Retention”, D. Flynn and A. Gibbons, Dec. 12, 2008, available from http://www.soccentral.com/results.asp?EntryID=27642;    2) “Dynamic State-Retention Flip-Flop for Fine-Grained Power Gating With Small Design and Power Overhead”, Stephan Henzler et al., IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 7, JULY 2006;    3) “Shaken or Stirred by Low Power Design Challenges?”, presented at ARM DevCon 2007, available from: http://www.synopsys.com/Solutions/EndSolutions/EclypseSolutions/CapsuleModule/a rm-snps_devcon_panel07.pdf;    4) “Case Study of a Low Power MTCMOS based ARM926 SoC”, Sachin Idgunji, Design, Analysis and Test Challenges, Lecture 2.3, International Test Conference 2007;    5) “Low Power Design”, Richard Goering, SCD source, September 2008, Issue 1, available from: http://www.leepr.com/PDF/SCDsource_STR_LowPower.pdf;    6) “Experimental Measurement of Novel Power Gating Structure with Intermediate Power Saving Mode”, Kim, Kosonocky et al., ISPLED '04, Aug. 9-11, 2004, Newport Beach, Calif., USA;    7) “Low Power Robust Computing Tutorial”, EECS, University of Michigan 2005, available at http://www.eecs.umich.eduktaustin/papers/MICR02005-tutorial.pdf;    8) “On-Demand Solution to Minimize I-Cache Leakage Energy with Maintaining Performance”, S. W. Chung and K. Skadron, IEEE Transactions on Computers, 57(1):7-24, January 2008, available at: http://www.cs.virginia.edu/˜skadron/Papers/icache_leakage_tc08.pdf;    9) “Standby Power Reduction Using Dynamic Voltage Scaling and Canary Flip-Flop Structures”, Benton H. Calhoun and Anantha P. Chandrakasan, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 9, SEPTEMBER 2004; and    10) U.S. patent application Ser. No. 12/385,674.